6T SRAM Cell
Static noise margin(SNM) is the noise voltage injected in the SRAM cell which results in flipping the bit values in hold or read state or opposite bit is written during the write operation. The 6T SRAM cell schematic is given in Fig.1.Fig.1. 6T SRAM Cell
The pair of transistors M1 and M2 make one inverter. The other pair M3 and M4 make another inverter. These inverters are connected back to back forming a flipflop. It stores one bit of information. The nmos transistor M5 and M6 are referred as access transistors as they are used to access node Q and QB when either read or write operations are performed on SRAM cell.
In a typical SRAM cell, the cell ratio CR is between 1.5 and 2 and the Pullup ratio, PR is between 0.7 and 1. We can first size access transistor and load transistor as they are the smallest size. We will consider about 600nm width for nmos. This will be typical width considering that we have to provide for the metal contact to source and drain. Thus M5 and M6 transistors will have W5/L5 =W6/L6= W/L= 600nm/180nm. W/L is ratio of channel width to channel length of transistor. The load transistor M2 and M4 will have W2/L2=W4/L4= W/L = 600nm/180nm. Assume PR=1.0. The driver transistors M1 and M3 will have W1/L1=W3/L3= W/L= 1000nm/180nm. CR= ~1.67>1.5.
The SNM in hold state is measured by plotting the dc transfer characteristics of the two inverters constituting the SRAM cell. The SNM in hold state is also referred as read margin. The WL voltage is kept low, implying access transistors M5 and M6 are in off state. The circuit schematic is given in fig 2.
Fig.2. The Circuit schematic 6T SRAM cell for hold margin
The simulation is performed in LTspice. The schematic used for simulation is shown in fig.3. Here WL , BL and BLB are kept at ground voltage. M5 and M6 can be disconnected from node Q and QB. The DC transfer characteristics are obtained for both inverters as shown in Fig.4.
Fig.3. The schematic used for simulation for determination of Hold Margin
Fig.4. The DC transfer characteristics of two inverters-hold state
The plot data is obtained from the LTSpice simulation as text file and plotted in EXCEL sheet as shown in Figure 5 for determination of SNM. In order to obtain the SNM, the DC transfer characteristics of the second inverter is transposed i.e Vin2 is plotted as a function of Vout2. The resultant plot is shown in Fig.6. This is called butterfly plot. The SNM can be determined by fitting biggest square between the two curves. The side of the square in Volts gives the SNM. The average of the size of the side of the two squares in two lobes of the butterfly plot is obtained. The SNM for the figure shown is about 0.6 Volts.
Fig.5. The butterfly plot of DC characteristics of two inverters in 6T SRAM cell.
Seevinck et. al. presented another method in which we can avoid plotting the graph using excel sheet and fitting by trial the square between the two transfer characteristics curves. We look at the graph of two curves in a coordinate system rotated by 45 degree. Next we plot the difference curve and find the maximum for read and hold margin. The height 'd' of the maxima gives the diagonal of the square. Thus
SNM = d /✔2.
This can be achieved by determining the inverter characteristics using a source voltage varying between -VDD/ and +Vdd/✔2. The coordinate transformation from X-Y axis to U-V axis gives us (X can be Vin1 or Vout2) and Y can be Vout1 or Vin2 respectively for two inverters Fig 6. (F1 made of M1-M3 and F2 made of M2-M4 of SRAM Fig. 7 ).
X= U cos45 + V sin45 =U/✔2 + V/✔2
Y = -U sin45+ V cos45 =-U/✔2 + V/✔2
These equations can be used to perform simulation and directly obtain the static noise margin.
Fig.6. DC transfer characteristics of inverter-1and inverter -2. The inverter -2 characteristics are transposed by plotting V(Vin2) vs V(Vout2).
The flip constituting SRAM is shown in Figure 6. We need to determine the DC characteristics of the two inverters F1 and F2 under different conditions depending on the SRAM states, hold state, read state and write state.
Source: https://en.wikichip.org/wiki/static_random-access_memory
The circuit for determination of DC characteristics are given in figure 8a and 8b. The input voltage is referred as X and the output voltage is Y.
Thus for inverter F1
Y= F1(X);
After substitution of Y and X in terms of U and V
-U/✔2 + V/✔2=F1(U/✔2 + V/✔2);
V = U + ✔2{F1(U/✔2 + V/✔2);
For inverter F2, we first mirror F2 about V axis.
X= F2'(Y) = F2(U/✔2 + V/✔2)
After mirroring about V axis.
U/✔2 + V/✔2= F2(-U/✔2 + V/✔2)
V/✔2= -U/✔2 +F2(-U/✔2 + V/✔2)
V = -U + ✔2 {F2(-U/✔2 + V/✔2)} ;
The circuits for simulation are shown in figure 8a and 8b.
Fig.8. The circuit schematic for determination of SNMThe DC characteristics are determined and the output voltage V1 and V2 are plotted. The difference abs(V1-V2) is obtained. The maximum value equals the ✔2 times SNM for hold and read mode. The minimum value equals ✔2 times SNM for write mode. The LTSPICE schematic used for direct determination of SNM in hold state is given in figure 9. The simulation results are shown in figure 10. The SNM is obtained by finding the average of the maximum values for the two maxima corresponding to two lobes of the butterfly plot. The SNM hold is 0.608 V.
Similar characteristics are obtain for determining SNM in read State. In order to determine SNM in Read State, the simulation is performed by emulating the read conditions. Thus BL and BLB is precharged high and WL is kept at Vdd. The LTspice schematic used for simulation is shown in fig.11. The simulation results are shown in figure 12. The SNM is obtained by finding the average of the maximum values for the two maxima corresponding to two lobes of the butterfly plot. The SNM read is 0.311 V.
Fig.11. The LTSPICE schematic for determination of Read Margin
Fig.12. The DC transfer characterstics Vx and Vy and the absolute difference in U-V coordinate system in read state.
In write state, the simulation is performed by emulating the write conditions. We will determine the SNM assuming we want to write 0. Thus WL is kept high and BL is kept at 0 volt and BLB is at VDD. The SNM in write state is also referred as write margin. The LTspice schematic used for simulation is shown in fig.13. We need to simulate to determine the range of U in the coordinate system for finding the minima. The simulation resulkts are shown in fig. 14. The U should be less then 0.2*.707 V .ie. about 0.15 volt.
Fig.13. The schematic used for simulation for determination of Write Margin
In order to determine directly from simulation the SNM in write mode we use the schematic as shown in fig. 15. The SNM in Write state is found to be 0.6 V.
Fig.14. The DC transfer characterstics Vx and Vy and the difference in U-V coordinate system in write state. The Vx values beyond 0.15 volts are not valid.
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