6T SRAM Cell:  Design and Simulation

Fig.1. 6T  SRAM Cell

                A SRAM cell stores one bit of information. 6T SRAM cell consist of six transistors as shown in figure 1. The pair of transistors M1 and M2  make one inverter . The other pair M3 and M4 make another inverter. These inverters are cross coupled and connected back to back forming a flip flop. The flip flop has two bistable states and each state represent stored values as bit 1 or bit 0. When bit 1 is stored, the voltage at node Q is VDD and node QB is 0 volts. When bit 0 is stored, the voltage at node Q is 0 volts  and node QB is at VDD. VDD is the power supply voltage. The nmos  transistors M1 and M3 are referred as driver transistors and pmos transistors M2 and M4 are the corresponding load transistors of inverters. The nmos  transistor M5 and M6 are referred as access transistors as they are used to access node Q and QB when either read or write operations are performed on SRAM cell. 

                In a typical SRAM cell, the ratio of the size of driver transistor to access transistor, referred as cell ratio, CR is between 1.5 and 2. This ensures read stability i.e. while reading the data from the SRAM cell, the data does not flip. This implies  W1/W5 = W3/W6 > 1.5, typically between  1.5 and 2.   

                The ratio of the size of load transistor to access transistor, referred as Pullup ratio, PR is between 0.7 and 1. This ensures write stability i.e. while writing the data, correct data is written and it does not flip. This implies  W2/W5 = W4/W6 < 1. Typically between  0.7 and 1.0.

                We can first size access transistor and load transistor as they are the smallest size. We will consider about 600nm width for nmos. This will be typical width considering that we have to provide for the metal contact to source and drain. Thus M5 and M6 transistors will have W5/L5 =W6/L6= W/L= 600nm/180nm. W/L is ratio of channel width to channel length of transistor. The load transistor M2 and M4 will have W2/L2=W4/L4= W/L = 600nm/180nm. Assume PR=1.0.  The driver transistors M1 and M3 will have W1/L1=W3/L3= W/L= 1000nm/180nm. CR= ~1.67>1.5. 

Next we will create a schematic of 6T SRAM cell and perform simulation.

 Click on LTspice to download  LTSPICE.  You can easily install it and run LTspice. 

                In order to simulate, we can create following schematic using component menu and choose nmos4, for transistors M1, M3. M5 and M6. By default the model name is nmos. This can be renamed as CMOSN.    Choose pmos4 for M2 and M5. The model name can be renamed as CMOSP The schematic looks like fig 2. All nodes are named. BL and BLB are the bitlines. They are used during read write operation. WL is wordline. VDD is supply voltage. We need to supply 1.8 volts. This also will be given as parameter. Q and QB are the nodes where we store the bit values. When Q=Vdd, Logic value 1 is stored. When Q= 0 volts, Logic 0 is stored. 

                The length and width of the transistors can be given as a parameter. The snapshot of model editor is given in fig.3.This helps in parametrizing the model and can be used with any other technology only by changing the mos model file. We are using here TSMC018.lib 180nm  mosfet  model file. This is included by giving the complete path in a spice statement. 

Spice statement for including the library file tsmc018.lib.

.lib "D:\LTspiceSLP\ltspice_course\lib\tsmc018.lib"

The mos model files are available at TSMC018.lib. 

Fig.3. Model Editor for 4 terminal mosfet 

                In this simulation, we have assumed that bitlines have a capacitance of about 0.5 pf and a resistance of about 10 ohms. They are also given as parameter. Parameter spice statement editor can be used to define the parameters or .param spice statement cane be used as shown in figure 4.  The complete schematic is shown in fig.4. 

Fig.4. Schematic of SRAM Cell for Read operation

            All the signals and supply voltage are included in the schematic using voltage component. It has many options to include various supply voltages. We have used pulse voltage waveform for WL and PC. 

SRAM Read Operation:

Here we perform simulation to demonstrate read operation. We need to precharge both bitlines BL and BLB to VDD. This is achieved by applying 0 volts to PC. This pulls up  both bitline BL and BLB to VDD.  

                Next in order to complete read operation we make WL to VDD. Initially WL = 0 volt. This is required for hold state of the SRAM. In hold state we maintain the the voltages at nodes Q and Qb. The read operation also should not flip the bit voltages. Appropriate pulse waveforms are applied to PC and WL and outputs are observed at BL and BLB. In this example V(Q) is VDD and V(Qb) is 0 volts. Hence BL remains at VDD and the voltage at BLB is reduced  by a small amount. In this example by about 400 mV. The difference is amplified by a sense amplifier. The sense amplifier output will be VDD or logic 1 if V(BL)> V(BLB) else at will be 0 Volts(Logic 0). The simulation results are shown in Fig.5. 

Fig.5. SRAM Read operation.

SRAM Write Operation:

                Here we perform simulation to demonstrate write operation. IF we want to write '1' to sram cell, we precharge BL to VDD and hold BLB to 0 volts.  This is achieved using the circuit schematic shown in Figure 6. Here WRITE_DATA, CS, PC and WL signals are used. 

            

                                   

                                   Fig.6. Schematic of SRAM Cell for Read/Write operation

            The data to be written is applied to WRITE_DATA. Initially the bitlines are precharged high by making PC low at 0 Volts. Next CS is enabled high. This pulls down one of the bitline BL or BLB depending on the WRITE_DATA. Eg. We intend to write bit '0' then WRITE_DATA will at 0 volts. Next CS is pulled high, this turns on the transistors M9 and M10. The bit line BL is pulled low. The Bitline BLB remains at VDD. Next we enable WL i.e. WL is made high.  If V(Q) is 0 , it will remain at 0 volts else if V(Q) is VDD (Logic '1'), it will be pulled low and Node Qb will be pulled high thus writing 0 in the SRAM Cell. After write operation WL is pulled low, followed by CS. The simulation results are shown in Fig.7. 

Fig.7. SRAM Write operation.